Computer Architecture Lab/SS2011

Project page for the course in summer 2011.

Group 1 AID

Nicolas Ingemann Borup

Jonas Andersen Dindorp

Cristian Pandele

Instruction Set 1

Summary and comparison between instruction sets of:

  1. MIPS
  2. ARM7
  3. LC3
  4. Zilog Z8

Document:

    Assignment1

    Architecture implementing decimal (AID)

    This page contains information about the implementation of a decimal processor in the course Advanced computer architecture on DTU

    Introduction

    Instruction set architecture

    We have several formats for the instruction set, as the operations needs different inputs

    Type 1:

    Instruction Opcode Destination register Source register Source register Usage


    add 0001 Rd Rs Rt Rd ← Rs + Rt
    mult 0011 Rd Rs Rt Rd ← upper part(Rs x Rt), Rd+1 ← lower part(Rs x Rt)
    sub 1010 Rd Rs Rt Rd ← Rs - Rt


    Type 2:

    Instruction Opcode Destination register Source register Source register Usage
    Immediate load 0010 Rd imm imm Rd ← imm


    Type 3:

    Instruction Opcode Destination register Source register Source register Usage
    shift left 0111 Rd Rs shamt Rd ← Rs << shamt
    shift right 1000 Rd Rs shamt Rd ← Rs >> shamt
    negation 1011 Rd Rs XXX Rd ← -Rs
    load 1110 Rd Rs imm Rd ← mem[Rs(imm)]
    store 1111 Rd Rs imm mem[Rd] ← Rs


    Type 4:

    Instruction Opcode Destination register Source register Source register Usage
    branch equal 1100 address flag value flag enabled if (flag value == ALU flags){next PC ← address}
    branch return 1101 address flag value flag enabled if (flag value == ALU flags){next PC ← address; push stack ← curr PC}


    Type 5:

    Instruction Opcode Destination register Source register Source register Usage
    jump to return 0110 XXX XXX XXX next PC ← pop stack
    nop 0000 XXX XXX XXX no operation

    Group 2 FooBarBaz fighters

    Mark Ruvald Pedersen

    Laust Brock-Nannestad

    Jaspur Højgaard

    Rasmus Bo Sørensen

    Assignment I

    Summary and comparison between instruction sets of:

    1. PIC16F84 microcontroller
    2. ARM
    3. Intel 80x86

    ISA / CPU Design

    Document (Assignment II):


    UART Exercise (Assignment III)

    Group 3 [Newbies]

    Ioannis Chionidis

    Georgios Papanikas

    Xia Hua

    Henning Dietmar Weiss

    Document:

    Group 4

    Andreas Erik Hindborg

    Niklas Quarfot Nielsen

    Tobias Jeppe

    Kristoffer Lyder Andersen

    Assignment 1

    Summary of:

    1. ARMv7-M
    2. PIC
    3. x86
    4. POWER7

    Document: https://www.campusnet.dtu.dk/cnnet/filesharing/ViewFileHistory.aspx?ElementId=347459&FolderId=567165&FileId=2700363

    Group ??

    Caroline Johannsen

    Assignment I

    ...

    Leros

    Martin Schoeberl (no group - this is just a template ;-)

    An FPGA optimized tiny processor core for utility functions (e.g., SW UART). The challenge is to get the resources below 500 LC and use just 2 RAM blocks. The processor is named after the Greek island Leros where the architecture was designed. Details of the design can be found at the Leros processor page.

    Perhaps I will do this design along the course to see how much work the assignment actually is ;-)


    Group 6

    Dimitrios Kosmadakis

    Assignment I

    Summary of:

    1. Intel 4004
    2. Intersil 9100
    3. TMS 9900
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